The present invention relates to a clock supply circuit built suitably into a custom IC such as a gate array, a cell based IC and the like.
A custom IC such as a gate array, a cell based IC and the like has been used, to meet required specifications at a low cost, for part of electric circuits in electronic apparatuses including a facsimile, printer, etc. Functions provided by custom ICs are various and their logical configurations are generally composed of a combinational circuit and a sequential circuit. In the combinational circuit, a value of an output signal is decided by only a value of an input signal and a timing of its output does not receive control. On the other hand, in the sequential circuit, a timing of its output is controlled by a clock signal externally inputted.
However, there have been following problems to be solved in the conventional technologies.
In general, a custom IC constituting an electric circuit in an electronic apparatus and being mounted on the electronic apparatus has been designed so that a plurality of functions is incorporated into one IC. Accordingly, in some cases, clocks each having a different frequency are used for a sequential circuit provided to each functional block. In these cases, a clock supply circuit receives a system clock fed by a clock generating circuit of the electronic apparatus and this clock supply circuit divides the system clock so that the divided clock has a frequency required for operations of each sequential circuit and supplies it to each functional block.
However, the custom ICs have been made large-scale and a block having a high operational clock frequency has been employed, causing increased power consumption of the whole custom ICs. Moreover, when the custom IC operates at a high frequency, increased noise components are emitted, presenting a problem that a rigorous and overall countermeasure against such a noise must be taken in a printed circuit board of the electronic apparatus or other devices incorporating the custom IC therein.
In view of the above, it is an object of the present invention to provide a clock supply circuit which allows reduction of power consumption in operations of a functional block using a clock signal having a high frequency and which allows solutions to a noise problem induced by a functional block using a clock signal having a high frequency.
According to an aspect of the present invention, there is provided a clock supply circuit for feeding a clock signal to a functional block of an electronic apparatus having a functional block operating based on a clock signal produced by dividing a system clock comprising:
a clock dividing section for generating the clock signal to be fed to the functional block by dividing the system clock; and
a control section for controlling a supply of the clock signal from the clock dividing section to the functional block depending on an active state of said functional block where a desired operation is required or on an idle state where no operation is required.
In the foregoing, a preferable mode is one wherein the clock dividing section is adapted to generate a plurality of clock signals each having a different frequency and wherein the control section comprises selectors adapted to selectively output the plural clock signals fed by the clock dividing section, and a decision section adapted to control a selection operation of the selectors so that, in an active state of the functional block where the desired operation is required, a clock signal selected out of the plural clock signals having proper frequency is supplied to ensure adequate operations of the functional block and so that, in an idle state, a clock signal having a frequency being lower than that of the clock supplied in the state where the desired operation is required is fed to the functional block.
Also, a preferable mode is one wherein the electronic apparatus is equipped with a plurality of functional blocks and wherein the clock dividing section is adapted to generate a plurality of clock signals each having a different frequency depending on each functional block and wherein each block is provided with each selector.
Also, a preferable mode is one wherein the control section is provided with a counter used for detecting the termination of the desired operation of each functional block and the frequency of a clock signal to be fed to each functional block the termination of the desired operation of which is detected by the counter is made lower by the decision section.
Also, a preferable mode is one wherein the control section is further provided with a gate circuit adapted to allow or not to allow a supply of the clock signal to the functional block and the operation of the gate circuit is so controlled by the decision section that, in an operational state of the functional block where the desired operation is required, the clock signal is supplied to the functional block to ensure proper operations of the functional block and that, in an idle state, the supply of the clock signal to the functional block is stopped.
Also, a preferable mode is one wherein the control section comprises a gate circuit adapted to allow or not to allow the supply of the clock signal outputted from the clock dividing section to the functional block and a decision circuit adapted to give control to operations of the gate circuit so that, in an active state of the functional block where the desired operation is required, the clock signal is supplied to the functional block to ensure proper operations of the functional block and that, in an idle state, the supply of said clock signal to said functional block is stopped.
Also, a preferable mode is one wherein the electronic apparatus is provided with a first functional block to control reading of data and a second functional block to control printing operations, having a facsimile function and copying function and wherein the dividing section is adapted to generate a clock signal having three kinds of frequencies, i.e., lowest frequency, highest frequency and intermediate frequency to be fed to the first and second functional blocks and the clock signal to be fed to the functional block according to the active state and idle state of the each functional block is selected out of the clock signal having the lowest, highest and intermediate frequencies with reference to each of operational modes including copying, sending and receiving operation modes of said electronic apparatus.
Also, a preferable mode is one wherein the electronic apparatus, in the copying operation mode, is adapted to supply a clock signal having the lowest frequency to the first functional block while it is in an idle state and to supply a clock signal having the highest frequency to the first functional block while it is in an active state, or to supply a clock signal having the lowest frequency to the second functional block while it is in an idle state and to supply a clock, signal having the highest frequency to the functional block while it is in an active state.
Also, a preferable mode is one wherein the electronic apparatus, in the sending operation mode, is adapted to supply a clock signal having the lowest frequency to the first functional block while it is in an idle state and to supply a clock signal having the intermediate frequency to the first functional block while it is in an active state, or to supply a clock signal having the lowest frequency to the second functional block regardless of whether the block is in an active or idle state.
Furthermore, a preferable mode is one wherein the electronic apparatus, in the receiving operation mode, is adapted to supply a clock signal having the lowest frequency to the first functional block regardless of whether the block is in an active or idle state, or to supply a clock signal having the lowest frequency to the second functional block while it is in an idle state and to supply a clock signal having the intermediate frequency to the second functional block while it is in an active state.